The present invention relates generally to communication receivers and, more specifically, to orthogonal frequency division multiplexing (OFDM) receivers.
The following disclosure will describe a digital video broadcasting (DVB) receiver for digital terrestrial television (DTV). The concepts are equally applicable to any other channels of transmission of DTV receivers and to other receivers or standards using orthogonal frequency division multiplexing (OFDM). These may include but not be limited to wireless standards worldwide such as wireless LAN 802.11a and g, HIPERLAN/2, Digital Audio Broadcasting (DAB), Digital Video Broadcasting Terrestrial (DVB-T), Digital Video Broadcasting for handheld (DVB-H), 802.16 Broadband Wireless Access, etc
The European terrestrial DTV standard DVB-T (ETS 300 744) is based on COFDM technologies to combat multipath fading. See ETSI EN 300 744 V.1.4.1 “Digital Video Broadcasting (DVB): Framing Structures, channel coding, and modulation for digital terrestrial television.” It specifies two operational modes:    1) A 2K mode based on 2048 FFT and having 1,705 carriers per OFDM symbol; and    2) An 8K mode based on 8192 FFT and having 6,817 carriers per OFDM symbol.
FIG. 1 shows a block diagram for a typical DVBT receiver. The digital signal processing for a DVBT receiver can be partitioned into three portions. The first portion 10 includes an RF front end 12, and A/D converter 14, an OFDM demodulator 16, a demodulation 18 and a pilot and TPS decoder 19. This receiver front-end signal processing portion performs receiver training, including various synchronization and channel estimation and OFDM demodulation. The second portion 20 is the DVBT receiver back-end signal processing block. It performs DVBT inner channel decoding and outer channel decoding. The third portion 30 is a MPEG Decoder. An example is shown in U.S. Pat. No. 6,359,938.
Due to computational complexity and high MIPs required for the DVBT receiver, until recently, DVBT receivers have been implemented in hardware using ASICs. In the case of multi-protocol communication systems, the hardware implementation becomes less attractive due to extra chip cost and PC board area consumed. In this disclosure, an improved software implementation of a DVBT receiver is described. In this design, all functions associated with the DVBT receiver may be implemented in software in the Sandbridge Technologies Multithreaded SB9600 processor. The device may be used in hand-held devices, such as mobile phones and PDAs.
The receiver includes an A/D converter for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator for producing a first set of complex I and Q components from the digital signal data stream and a guard segment length detector using the first set of I and Q components. It further includes an extractor for identifying and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.
The FFT demodulator is an orthogonal frequency division multiplexing demodulator and the receiver may be a digital video broadcasting receiver. The FFT demodulator demodulates two symbols at one time to produce the second sets of complex I and Q components. A processor is programmed to operate as the I/Q demodulator, the guard segment length detector, the extractor, and the FFT demodulator. The FFT demodulator is an orthogonal frequency division multiplexing demodulator, and the receiver may be a digital video broadcasting receiver.
The receiver may include at least two antennas each connected to a respective receiver front-end and A/D converter. The at least two antennas are orthogonally positioned and the receiver front-end includes a phase shifter.
The receiver includes a first carrier signal offset estimator and a first symbol synchronizing signal generator, each using the first set of I and Q components, to estimate the offset of the carrier signal and adjusting the A/D converter and to generate a symbol synchronizing signal for the extractor, respectively, at least during an initialization phase of the receiver. The I/Q demodulator, the guard segment length detector, the first carrier signal offset estimator, and the first symbol synchronizing signal generator operate only during the initialization phase of the receiver. The receiver includes a second carrier signal offset estimator and a second symbol synchronizing signal generator, each using the second sets of I and Q components from the FFT demodulator, to estimate the offset of the carrier signal and adjusting the A/D converter and to generate a symbol synchronizing signal for the extractor, respectively, at least after an initialization phase of the receiver.
These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings.